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sy89218u precision 1:15 lvds fa nout buffer with 2:1 mux and four 1/2/4 clock divider output banks precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com august 2007 m9999-082407- c hbwhelp@micrel.com or (408) 955-1690 general description the sy89218u is a 2.5v precision, high-speed, integrated clock divider and lvds fanout buffer capable of handling clocks up to 1.5ghz. optimized for communications applications, the four independently controlled output banks are phase-matched and can be configured for pass through (1) , 2 or 4 divider ratios. the differential input includes micrel?s unique, 3-pin input termination architecture that allows the user to interface to any differential signal (ac- or dc-coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor netwo rks in the signal path. the low-skew, low-jitter outputs are lvds compatible with extremely fast rise/fall times guaranteed to be less than 200ps. the /mr (master reset) input asynchronously resets the outputs. a four-clock delay a fter de-asserting /mr allows the counters to synchronize and start the outputs from the same state without any runt pulse. the sy89218u is part of micrel?s precision edge ? product family. all support documentation can be found at micrel's web site at: www.micrel.com . features ? low-skew lvds output banks with independently programmable 1, 2 and 4 divider options ? four output banks, 15 total outputs ? guaranteed ac performance over temperature and voltage: ? accepts a clock fr equency up to 1.5ghz ? <1600ps in-to-out propagation delay ? <200ps rise/fall time ? <35ps within bank skew ? fail safe input ? prevents outputs from oscillating ? ultra-low jitter design: ? <1ps rms random jitter ? <10ps pp total jitter (clock) ? patent-pending input termination and vt pin accepts dc- and ac-coupled inputs (cml, pecl, lvds) ? lvds-compatible outputs ? cmos/ttl-compatible output enable (en) and divider select control ? 2.5v 5% power supply ? ?40c to +85c temperature range ? available in 64-pin tqfp applications ? all sonet/sdh applications ? all fibre channel applications ? all gigabit ethernet applications markets ? lan/wan rout ers/switches ? storage ? ate ? test and measurement
micrel, inc. sy89218u august 2007 2 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 functional block diagram
micrel, inc. sy89218u august 2007 3 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish sy89218uhy t64-1 industrial sy89218uhy with pb-free bar-line indicator pb-free matte-sn SY89218UHYTR (2) t64-1 industrial sy89218uhy with pb-free bar-line indicator pb-free matte-sn notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 64-pin epad-tqfp (t64-1)
micrel, inc. sy89218u august 2007 4 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 1, 2 3, 4 15, 16 17, 18 fsela1, fsela0 fselb1, fselb0 fselc1, fselc0 fseld1, fseld0 single-ended inputs: these ttl/cmos inputs select the divide ratio for each of the four banks of outputs. note that each of these inputs is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. the input-switching threshold is v cc /2. 5, 8, 11, 14 in0, /in0 in1, /in1 differential inputs: these input pairs are the differential signal inputs to the device. these inputs accept ac- or dc-coupled s ignals as small as 100mv. the input pairs internally terminate to a vt pin through 50 ? . note that these inputs will default to an indeterminate state if left open. please re fer to the ?input interface applications? section for more details. 6, 12 vt0, vt1 input termination center-tap: each side of a differential input pair terminates to a vt pin. the vt pin provides a center-tap to a termination network for maximum interface flexibility. see ? input interface applications? section for more details. 7, 13 vref-ac0, vref-ac1 reference voltage: these outputs bias to v cc ?1.2v. they are used for ac-coupling inputs in and /in. connect vref-ac directly to the corresponding vt pin. bypass with 0.01f low esr capacitor to vcc. due to li mited drive capability, the vref-ac pin is only intended to drive its respective vt pi n. maximum sink/source current is 1.5ma. please refer to the ?input interface ap plications? section for more details. 9 /mr single-ended input: this ttl/cmos-compatible master reset function asynchronously sets the true outputs low, complimentary out puts high, and holds them in that state as long as /mr remains low. this input is internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. the input-switching threshold is v cc /2. 10 clk_sel single-ended input: this single-ended ttl/cm os-compatible input selects the inputs to the multiplexer. note that this input is internally connected to a 25k ? pull-up resistor and will default to logic high state if le ft open. the input-switching threshold is v cc /2. 20, 25, 30, 33, 40 41, 48, 50, 55, 62 vcc positive power supply. bypass with a 0.1f||0.01f low esr capacitor as close to v cc pin as possible. 21, 22 23, 24 26, 27 28, 29 /qc0, qc0 /qc1, qc1 /qc2, qc2 /qc3, qc3 bank c lvds differential output pairs controlled by fselc1 and fselc0. refer to ?function table? for details. unused output pairs should be terminated with 100 ? across the differential pair 31 nc no connect. 34, 35, 36, 37 38, 39, 42, 43 44, 45, 46, 47 /qd0, qd0 /qd1, qd1 /qd2, qd2 /qd3, qd3 /qd4, qd4 /qd5, qd5 bank d lvds differential output pairs controlled by fseld1 and fseld0. refer to ?function table? for details. unused output pairs should be terminated with 100 ? across the differential pair 51, 52 53, 54 /qa0, qa0 /qa1, qa1 bank a lvds differential output pairs controlled by fsela1 and fsela0. refer to ?function table? for details. unused output pairs should be terminated with 100 ? across the differential pair 56, 57 58, 59 60, 61 /qb0, qb0 /qb1, qb1 /qb2, qb2 bank b lvds differential output pairs controlled by fselb1 and fselb0. refer to ?function table? for details. unused output pairs should be terminated with 100 ? across the differential pair
micrel, inc. sy89218u august 2007 5 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 pin description (continued) pin number pin name pin function 64 en single-ended input: this ttl/cmos input di sables and enables the outputs. it is internally connected to a 25k ? pull-up resistor and will default to logic high state if left open. when disabled, true outputs go low and complementary outputs switch to high. the input switching threshold is v cc /2. for the input enable and disable functional description, refer to figures 2d and 2e. 19, 32, 49, 63 gnd, exposed pad ground and exposed pad must be connected to the same gnd plane on the board. function table /mr (1) en (2, 3) clk_sel fselx0 (4) fselx1 (4) q 1 1 0 0 0 in01 1 1 1 0 0 in11 1 1 0 1 0 in02 1 1 1 1 0 in12 1 1 0 x 1 in04 1 1 1 x 1 in14 1 0 x x x 0 0 x x x x 0 notes: 1. /mr asynchronously forces q to low (/q to high). 2. en forces q low between 2 and 6 input clock cycles a fter the falling edge of en. refer to ?timing diagram? section. 3. en synchronously enables q between two and six input clock cycl es after the rising edge of en. refer to ?timing diagram? sec tion. 4. fsel valid for each of the banks a, b, c, and d. banks can be programmed independent of each other.
micrel, inc. sy89218u august 2007 6 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ) ............................... ?0.5v to +4.0v input voltage (v in ) .......................................?0.5v to v cc termination current source or sink current on v t ........................100ma input current source or sink current on in, /in ...................50ma v ref-ac current (3) source or sink current on v ref-ac ....................2ma operating ratings (2) supply voltage (v in )..................... +2.375v to +2.625v ambient temperature (t a ) .................. ?40c to +85c package thermal resistance (4) tqfp still-air ( ja ) ............................................35c/w junction-to-board ( jb ) ..........................20c/w lead temperature (soldering, 20sec.)?????.260c storage temperature (t s )?????...?65c to +150c dc electrical characteristics (5) v cc = +2.5v 5%, t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units v cc positive supply voltage range 2.375 2.625 v i cc power supply current 325 420 ma r diff_in differential input resistance (in-to-/in) 90 100 110 ? r in input resistance (in-to-v t , /in-to-v t ) 45 50 55 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ?0.1 v v in input voltage swing (in, /in) s ee figure 1a, note 6 0.1 2.5 v v diff_in differential input voltage swing |in ? /in| see figure 1b 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v ref-ac reference voltage v cc ?1.3 v cc ?1.2 v cc ?1.1 v v t_in voltage from input to v t 1.28 v lvttl/cmos dc electri cal characteristics (5) v cc = +2.5v 5%, t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2 v v il input low voltage 0.8 v i ih input high current ?125 30 a i il input low current -300 a notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ra tings conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. due to the limited drive capability use for input of the same package only. 4. jb and ja values are determined for a 4-layer board in still-air number, unless otherwise stated. 5. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 6. v in (max) is specified when v t is floating.
micrel, inc. sy89218u august 2007 7 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 lvds outputs dc electrical characteristics (7) v cc = +2.5v 5%, r l = 100 ? across the outputs; t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units v out output voltage swing (q, /q) see figure 1a 250 325 mv v diff_out differential output voltage swing |q ? /q| see figure 1b 500 650 mv v ocm output common mode voltage (q, /q) see figure 5b 1.125 1.20 1.275 v ? v ocm change in common mode voltage (q, /q) see figure 5b ?50 +50 mv notes: 7. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. sy89218u august 2007 8 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (8) v cc = +2.5v 5%, r l = 100 ? across the outputs; t a = ?40c to +85c, unl ess otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency v out 200mv 1.5 2 ghz in-to-q 800 1250 1600 ps clk_sel-to-q 700 1000 1400 ps t pd differential propagation delay /mr(h-l)-to-q 700 1000 1400 ps t rr reset recovery time /mr (l-h)-to-in 300 ps t pd tempco differential propagation delay temperature coefficient 225 fs/c within-bank skew within same fanout bank (9. 10) 35 ps bank-to-bank skew same divide setting (11) 40 ps bank-to-bank skew different divide setting (11) 60 ps t skew part-to-part skew note 12 400 ps random jitter (rj) note 13 1 ps rms total jitter (tj) note 14 10 ps pp t jitter cycle-to-cycle jitter note 15 1 ps rms t r, t f output rise/fall time (20% to 80%) at full output swing 60 120 200 ps divide-by-2 or divide-by-4 47 53 % divide-by-1, input > 1ghz 45 55 % duty cycle divide-by-1, input < 1ghz 47 53 % notes: 8. measured with 100mv input swing. input t r, /t f < 300ps. see ?timing diagrams? section for def inition of parameters. high-frequency ac- parameters are guaranteed by design and characterization. 9. within-bank skew is the difference in propagat ion delays among the outputs within the same bank. 10. skews within banks depend on the number of outputs. with in-bank skew decreases if the bank has lesser outputs. 11. bank-to-bank skew is the difference in propagation delays betw een outputs from different banks. bank-to-bank skew is also t he phase offset between each bank, after mr is applied. 12. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs. 13. random jitter is measured with a k 28.7 comma detect character pattern. 14. total jitter definition: with an ideal clock input frequency f max , no more than one output edge in 10 12 output edges will deviate by more than the specified peak-to-peak jitter value. 15. cycle-to-cycle jitter definition: the va riation of periods between adjacent cycles, t n ?t n?1 where t is the time between rising edges of the output signal.
micrel, inc. sy89218u august 2007 9 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 functional description clock select (clk_sel) clk_sel is an asynchronous ttl/cmos compatible input that selects one of t he two input signals. internal 25k ? pull-up resistor defaults the input to logic high if left open. delay between the clock selection and multiplexer selecting the correct input signal depends upon the divider settings. the delay varies due to the asynchronous nature of the input. input switching threshold is v cc /2. refer to figure 2a. fail-safe input (fsi) the input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mv pk (200mv pp ), typically 30mv pk . maximum frequency of the sy89218u is limited by the fsi function. refer to figure 2b. input clock failure case if the input clock fails to a fl oating, static, or extremely low signal swing, the fsi function will eliminate a metastable condition and guarantee a stable output signal. no ringing and no undetermined state will occur at the output under these conditions. please note that the fsi func tion will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. d ue to the fsi function, the propagation delay w ill depend upon rise and fall time of the input signal and on its amplitude. refer to ?typical operating charac teristics? for detailed information. master reset (/mr) /mr is a ttl/cmos compatible input that resets the output signals. internal 25k ? pull-up resistor defaults the input to logic high if left open. a low input to /mr asynchronously sets the true outputs low and complimentary outputs high. the outputs will remain in this state until /mr is forced high. input switching threshold is v cc /2. refer to figure 2c. enable outputs (en) en is a synchronous ttl/cmos compatible input that enables/disables the outputs based on the input to this pin. internal 25k ? pull-up resistor defaults the input to logic high if left open. a logic low input causes the true outputs to go low and complementary outputs to go high. it takes 2 to 6 input clock cycles before the outputs are enabled/disabled because the signals are going through a series of flip-flops. input switching threshold is v cc /2. refer to figure 2d and 2e.
micrel, inc. sy89218u august 2007 10 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 single-ended diffe rential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing timing diagrams figure 2a. propagation delay figure 2b. fail safe feature
micrel, inc. sy89218u august 2007 11 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 timing diagrams figure 2c. reset with output enabled
micrel, inc. sy89218u august 2007 12 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 timing diagrams figure 2d. enable timing figure 2e. disable timing
micrel, inc. sy89218u august 2007 13 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 2.5v, gnd = 0v, v in = 100mv, r l = 100 ? across the outputs, t a = 25c, unless otherwise stated.
micrel, inc. sy89218u august 2007 14 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 functional characteristics v cc = 2.5v, gnd = 0v, v in = 100mv, r l = 100 ? across the outputs, t a = 25c, unless otherwise stated.
micrel, inc. sy89218u august 2007 15 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 input stage internal termination figure 3. simplified di fferential input stage input interface applications figure 4a. cml interface (dc-coupled) option: may connect v t to vcc figure 4b. cml interface (ac-coupled) figure 4c. lvpecl interface (dc-coupled) figure 4d. lvpecl interface (ac-coupled) figure 4e. lvds interface
micrel, inc. sy89218u august 2007 16 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 lvds output interface applications lvds specifies a small swing of 325mv typical, on a nominal 1.2v common mode above ground. the common mode voltage has tight limits to permit large variations in the ground between and lvds driver and receiver. also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep emi low. figure 5a. lvds differential measurement figure 5b. lvds common mode measurement related product and su pport documentation part number function data sheet link sy89221u precision 1:15 lvpecl fanout buffer with 2:1 mux and four 1/2/4 clock divider output banks http://www.micrel.com/_p df/hbw/sy89221u.pdf sy89200u ultra-precision 1:8 lvds fanout with three 1/2/4 clock divider output banks http://www.micrel.com/_p df/hbw/sy89200u.pdf sy89202u ultra-precision 1:8 lvpecl fanout with three 1/2/4 clock divider output banks http://www.micrel.com/_p df/hbw/sy89202u.pdf hbw solutions new products and applications http://www.micrel.com/page.do?page=/product- info/as/hbwsolutions.shtml
micrel, inc. sy89218u august 2007 17 m9999-082407-c hbwhelp@micrel.com or (408) 955-1690 package information 64-pin epad-tqfp (t64-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life s upport appliances, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2006 micrel , incor p orated.

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